Freescale Semiconductor /MKM34ZA5 /SIM /SCGC6

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as SCGC6

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (0)FTFA 0 (0)DMAMUX0 0 (0)DMAMUX1 0 (0)DMAMUX2 0 (0)DMAMUX3 0 (0)RNGA 0 (0)ADC 0 (0)PIT0 0 (0)PIT1 0 (0)AFE 0 (0)CRC 0 (0)LPTMR 0 (0)SIM_LP 0 (SIM_HP)SIM_HP

FTFA=0, PIT1=0, LPTMR=0, SIM_LP=0, RNGA=0, DMAMUX2=0, CRC=0, PIT0=0, ADC=0, AFE=0, DMAMUX0=0, DMAMUX3=0, DMAMUX1=0

Description

System Clock Gating Control Register 6

Fields

FTFA

FTFA Clock Gate Control

0 (0): Clock disabled

1 (1): Clock enabled

DMAMUX0

DMA MUX0 Clock Gate Control

0 (0): Clock disabled

1 (1): Clock enabled

DMAMUX1

DMA MUX1 Clock Gate Control

0 (0): Clock disabled

1 (1): Clock enabled

DMAMUX2

DMA MUX2 Clock Gate Control

0 (0): Clock disabled

1 (1): Clock enabled

DMAMUX3

DMA MUX3 Clock Gate Control

0 (0): Clock disabled

1 (1): Clock enabled

RNGA

RNGA Clock Gate Control

0 (0): Clock disabled

1 (1): Clock enabled

ADC

SAR ADC Clock Gate Control

0 (0): Clock disabled

1 (1): Clock enabled

PIT0

PIT0 Clock Gate Control

0 (0): Clock disabled

1 (1): Clock enabled

PIT1

PIT1 Clock Gate Control

0 (0): Clock disabled

1 (1): Clock enabled

AFE

AFE Clock Gate Control

0 (0): Clock disabled

1 (1): Clock enabled

CRC

Programmable CRC Clock Gate Control

0 (0): Clock disabled

1 (1): Clock enabled

LPTMR

LPTMR Clock Gate Control

0 (0): Clock disabled

1 (1): Clock enabled

SIM_LP

SIM_LP Clock Gate Control

0 (0): Clock is disabled

1 (1): Clock is enabled

SIM_HP

SIM_HP Clock Gate Control

1 (1): Clock is always enabled to SIM

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